// $Module: sc_odma $
// $RegisterBank Version: V 1.0.00 $
// $Author:  $
// $Date: Mon, 13 Sep 2021 11:45:47 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  SC_ODMA_ODMA_REG_00  0x0
#define  SC_ODMA_ODMA_REG_01  0x4
#define  SC_ODMA_ODMA_REG_02  0x8
#define  SC_ODMA_ODMA_REG_03  0xc
#define  SC_ODMA_ODMA_REG_04  0x10
#define  SC_ODMA_ODMA_REG_05  0x14
#define  SC_ODMA_ODMA_REG_06  0x18
#define  SC_ODMA_ODMA_REG_07  0x1c
#define  SC_ODMA_ODMA_REG_08  0x20
#define  SC_ODMA_ODMA_REG_09  0x24
#define  SC_ODMA_ODMA_REG_10  0x28
#define  SC_ODMA_ODMA_REG_11  0x2c
#define  SC_ODMA_ODMA_REG_12  0x30
#define  SC_ODMA_ODMA_REG_13  0x34
#define  SC_ODMA_ODMA_REG_14  0x38
#define  SC_ODMA_ODMA_REG_15  0x3c
#define  SC_ODMA_ODMA_REG_16  0x40
#define  SC_ODMA_SB_REG_CTRL  0x50
#define  SC_ODMA_SB_REG_C_STAT  0x54
#define  SC_ODMA_SB_REG_Y_STAT  0x58
#define  SC_ODMA_SC_CSC_REG_00  0x100
#define  SC_ODMA_SC_CSC_REG_01  0x104
#define  SC_ODMA_SC_CSC_REG_02  0x108
#define  SC_ODMA_SC_CSC_REG_03  0x10c
#define  SC_ODMA_SC_CSC_REG_04  0x110
#define  SC_ODMA_SC_CSC_REG_05  0x114
#define  SC_ODMA_SC_CSC_REG_06  0x118
#define  SC_ODMA_SC_CSC_REG_07  0x11c
#define  SC_ODMA_SC_CSC_REG_08  0x120
#define  SC_ODMA_REG_DMA_BLEN   0x0
#define  SC_ODMA_REG_DMA_BLEN_OFFSET 0
#define  SC_ODMA_REG_DMA_BLEN_MASK   0x1
#define  SC_ODMA_REG_FMT_SEL   0x0
#define  SC_ODMA_REG_FMT_SEL_OFFSET 8
#define  SC_ODMA_REG_FMT_SEL_MASK   0xf00
#define  SC_ODMA_REG_SC_ODMA_HFLIP   0x0
#define  SC_ODMA_REG_SC_ODMA_HFLIP_OFFSET 16
#define  SC_ODMA_REG_SC_ODMA_HFLIP_MASK   0x10000
#define  SC_ODMA_REG_SC_ODMA_VFLIP   0x0
#define  SC_ODMA_REG_SC_ODMA_VFLIP_OFFSET 17
#define  SC_ODMA_REG_SC_ODMA_VFLIP_MASK   0x20000
#define  SC_ODMA_REG_SC_422_AVG   0x0
#define  SC_ODMA_REG_SC_422_AVG_OFFSET 20
#define  SC_ODMA_REG_SC_422_AVG_MASK   0x100000
#define  SC_ODMA_REG_SC_420_AVG   0x0
#define  SC_ODMA_REG_SC_420_AVG_OFFSET 21
#define  SC_ODMA_REG_SC_420_AVG_MASK   0x200000
#define  SC_ODMA_REG_C_ROUND_MODE   0x0
#define  SC_ODMA_REG_C_ROUND_MODE_OFFSET 22
#define  SC_ODMA_REG_C_ROUND_MODE_MASK   0x400000
#define  SC_ODMA_REG_BF16_EN   0x0
#define  SC_ODMA_REG_BF16_EN_OFFSET 23
#define  SC_ODMA_REG_BF16_EN_MASK   0x800000
#define  SC_ODMA_REG_DMA_Y_BASE_LOW_PART   0x4
#define  SC_ODMA_REG_DMA_Y_BASE_LOW_PART_OFFSET 0
#define  SC_ODMA_REG_DMA_Y_BASE_LOW_PART_MASK   0xffffffff
#define  SC_ODMA_REG_DMA_Y_BASE_HIGH_PART   0x8
#define  SC_ODMA_REG_DMA_Y_BASE_HIGH_PART_OFFSET 0
#define  SC_ODMA_REG_DMA_Y_BASE_HIGH_PART_MASK   0xff
#define  SC_ODMA_REG_DMA_U_BASE_LOW_PART   0xc
#define  SC_ODMA_REG_DMA_U_BASE_LOW_PART_OFFSET 0
#define  SC_ODMA_REG_DMA_U_BASE_LOW_PART_MASK   0xffffffff
#define  SC_ODMA_REG_DMA_U_BASE_HIGH_PART   0x10
#define  SC_ODMA_REG_DMA_U_BASE_HIGH_PART_OFFSET 0
#define  SC_ODMA_REG_DMA_U_BASE_HIGH_PART_MASK   0xff
#define  SC_ODMA_REG_DMA_V_BASE_LOW_PART   0x14
#define  SC_ODMA_REG_DMA_V_BASE_LOW_PART_OFFSET 0
#define  SC_ODMA_REG_DMA_V_BASE_LOW_PART_MASK   0xffffffff
#define  SC_ODMA_REG_DMA_V_BASE_HIGH_PART   0x18
#define  SC_ODMA_REG_DMA_V_BASE_HIGH_PART_OFFSET 0
#define  SC_ODMA_REG_DMA_V_BASE_HIGH_PART_MASK   0xff
#define  SC_ODMA_REG_DMA_Y_PITCH   0x1c
#define  SC_ODMA_REG_DMA_Y_PITCH_OFFSET 0
#define  SC_ODMA_REG_DMA_Y_PITCH_MASK   0xffffff
#define  SC_ODMA_REG_DMA_C_PITCH   0x20
#define  SC_ODMA_REG_DMA_C_PITCH_OFFSET 0
#define  SC_ODMA_REG_DMA_C_PITCH_MASK   0xffffff
#define  SC_ODMA_REG_DMA_X_STR   0x24
#define  SC_ODMA_REG_DMA_X_STR_OFFSET 0
#define  SC_ODMA_REG_DMA_X_STR_MASK   0xfff
#define  SC_ODMA_REG_DMA_Y_STR   0x28
#define  SC_ODMA_REG_DMA_Y_STR_OFFSET 0
#define  SC_ODMA_REG_DMA_Y_STR_MASK   0xfff
#define  SC_ODMA_REG_DMA_WD   0x2c
#define  SC_ODMA_REG_DMA_WD_OFFSET 0
#define  SC_ODMA_REG_DMA_WD_MASK   0xfff
#define  SC_ODMA_REG_DMA_HT   0x30
#define  SC_ODMA_REG_DMA_HT_OFFSET 0
#define  SC_ODMA_REG_DMA_HT_MASK   0xfff
#define  SC_ODMA_REG_DMA_DEBUG   0x34
#define  SC_ODMA_REG_DMA_DEBUG_OFFSET 0
#define  SC_ODMA_REG_DMA_DEBUG_MASK   0xffffffff
#define  SC_ODMA_REG_DMA_INT_LINE_TARGET   0x38
#define  SC_ODMA_REG_DMA_INT_LINE_TARGET_OFFSET 0
#define  SC_ODMA_REG_DMA_INT_LINE_TARGET_MASK   0xfff
#define  SC_ODMA_REG_DMA_INT_LINE_TARGET_SEL   0x38
#define  SC_ODMA_REG_DMA_INT_LINE_TARGET_SEL_OFFSET 16
#define  SC_ODMA_REG_DMA_INT_LINE_TARGET_SEL_MASK   0x30000
#define  SC_ODMA_REG_DMA_INT_CYCLE_LINE_TARGET   0x3c
#define  SC_ODMA_REG_DMA_INT_CYCLE_LINE_TARGET_OFFSET 0
#define  SC_ODMA_REG_DMA_INT_CYCLE_LINE_TARGET_MASK   0x7ff
#define  SC_ODMA_REG_DMA_INT_CYCLE_LINE_TARGET_SEL   0x3c
#define  SC_ODMA_REG_DMA_INT_CYCLE_LINE_TARGET_SEL_OFFSET 16
#define  SC_ODMA_REG_DMA_INT_CYCLE_LINE_TARGET_SEL_MASK   0x30000
#define  SC_ODMA_REG_DMA_LATCH_LINE_CNT   0x40
#define  SC_ODMA_REG_DMA_LATCH_LINE_CNT_OFFSET 0
#define  SC_ODMA_REG_DMA_LATCH_LINE_CNT_MASK   0x1
#define  SC_ODMA_REG_DMA_LATCHED_LINE_CNT   0x40
#define  SC_ODMA_REG_DMA_LATCHED_LINE_CNT_OFFSET 8
#define  SC_ODMA_REG_DMA_LATCHED_LINE_CNT_MASK   0xfff00
#define  SC_ODMA_REG_SB_MODE   0x50
#define  SC_ODMA_REG_SB_MODE_OFFSET 0
#define  SC_ODMA_REG_SB_MODE_MASK   0x3
#define  SC_ODMA_REG_SB_SIZE   0x50
#define  SC_ODMA_REG_SB_SIZE_OFFSET 2
#define  SC_ODMA_REG_SB_SIZE_MASK   0x4
#define  SC_ODMA_REG_SB_NB   0x50
#define  SC_ODMA_REG_SB_NB_OFFSET 8
#define  SC_ODMA_REG_SB_NB_MASK   0x1f00
#define  SC_ODMA_REG_SB_FULL_NB   0x50
#define  SC_ODMA_REG_SB_FULL_NB_OFFSET 16
#define  SC_ODMA_REG_SB_FULL_NB_MASK   0x1f0000
#define  SC_ODMA_REG_SB_SW_WPTR   0x50
#define  SC_ODMA_REG_SB_SW_WPTR_OFFSET 24
#define  SC_ODMA_REG_SB_SW_WPTR_MASK   0x1f000000
#define  SC_ODMA_REG_SB_SET_STR   0x50
#define  SC_ODMA_REG_SB_SET_STR_OFFSET 30
#define  SC_ODMA_REG_SB_SET_STR_MASK   0x40000000
#define  SC_ODMA_REG_SB_SW_CLR   0x50
#define  SC_ODMA_REG_SB_SW_CLR_OFFSET 31
#define  SC_ODMA_REG_SB_SW_CLR_MASK   0x80000000
#define  SC_ODMA_REG_U_SB_WPTR_RO   0x54
#define  SC_ODMA_REG_U_SB_WPTR_RO_OFFSET 0
#define  SC_ODMA_REG_U_SB_WPTR_RO_MASK   0x1f
#define  SC_ODMA_REG_U_SB_FULL   0x54
#define  SC_ODMA_REG_U_SB_FULL_OFFSET 6
#define  SC_ODMA_REG_U_SB_FULL_MASK   0x40
#define  SC_ODMA_REG_U_SB_EMPTY   0x54
#define  SC_ODMA_REG_U_SB_EMPTY_OFFSET 7
#define  SC_ODMA_REG_U_SB_EMPTY_MASK   0x80
#define  SC_ODMA_REG_U_SB_DPTR_RO   0x54
#define  SC_ODMA_REG_U_SB_DPTR_RO_OFFSET 8
#define  SC_ODMA_REG_U_SB_DPTR_RO_MASK   0x3f00
#define  SC_ODMA_REG_V_SB_WPTR_RO   0x54
#define  SC_ODMA_REG_V_SB_WPTR_RO_OFFSET 16
#define  SC_ODMA_REG_V_SB_WPTR_RO_MASK   0x1f0000
#define  SC_ODMA_REG_V_SB_FULL   0x54
#define  SC_ODMA_REG_V_SB_FULL_OFFSET 22
#define  SC_ODMA_REG_V_SB_FULL_MASK   0x400000
#define  SC_ODMA_REG_V_SB_EMPTY   0x54
#define  SC_ODMA_REG_V_SB_EMPTY_OFFSET 23
#define  SC_ODMA_REG_V_SB_EMPTY_MASK   0x800000
#define  SC_ODMA_REG_V_SB_DPTR_RO   0x54
#define  SC_ODMA_REG_V_SB_DPTR_RO_OFFSET 24
#define  SC_ODMA_REG_V_SB_DPTR_RO_MASK   0x3f000000
#define  SC_ODMA_REG_Y_SB_WPTR_RO   0x58
#define  SC_ODMA_REG_Y_SB_WPTR_RO_OFFSET 0
#define  SC_ODMA_REG_Y_SB_WPTR_RO_MASK   0x1f
#define  SC_ODMA_REG_Y_SB_FULL   0x58
#define  SC_ODMA_REG_Y_SB_FULL_OFFSET 6
#define  SC_ODMA_REG_Y_SB_FULL_MASK   0x40
#define  SC_ODMA_REG_Y_SB_EMPTY   0x58
#define  SC_ODMA_REG_Y_SB_EMPTY_OFFSET 7
#define  SC_ODMA_REG_Y_SB_EMPTY_MASK   0x80
#define  SC_ODMA_REG_Y_SB_DPTR_RO   0x58
#define  SC_ODMA_REG_Y_SB_DPTR_RO_OFFSET 8
#define  SC_ODMA_REG_Y_SB_DPTR_RO_MASK   0x3f00
#define  SC_ODMA_REG_SB_FULL   0x58
#define  SC_ODMA_REG_SB_FULL_OFFSET 15
#define  SC_ODMA_REG_SB_FULL_MASK   0x8000
#define  SC_ODMA_REG_SC_CSC_EN   0x100
#define  SC_ODMA_REG_SC_CSC_EN_OFFSET 0
#define  SC_ODMA_REG_SC_CSC_EN_MASK   0x1
#define  SC_ODMA_REG_SC_CSC_Q_MODE   0x100
#define  SC_ODMA_REG_SC_CSC_Q_MODE_OFFSET 1
#define  SC_ODMA_REG_SC_CSC_Q_MODE_MASK   0x2
#define  SC_ODMA_REG_SC_CSC_Q_DROP   0x100
#define  SC_ODMA_REG_SC_CSC_Q_DROP_OFFSET 2
#define  SC_ODMA_REG_SC_CSC_Q_DROP_MASK   0xc
#define  SC_ODMA_REG_SC_HSV_EN   0x100
#define  SC_ODMA_REG_SC_HSV_EN_OFFSET 4
#define  SC_ODMA_REG_SC_HSV_EN_MASK   0x10
#define  SC_ODMA_REG_SC_HSV_FLOOR_EN   0x100
#define  SC_ODMA_REG_SC_HSV_FLOOR_EN_OFFSET 5
#define  SC_ODMA_REG_SC_HSV_FLOOR_EN_MASK   0x20
#define  SC_ODMA_REG_SC_CSC_BD_DIS   0x100
#define  SC_ODMA_REG_SC_CSC_BD_DIS_OFFSET 8
#define  SC_ODMA_REG_SC_CSC_BD_DIS_MASK   0x100
#define  SC_ODMA_REG_SC_HSV_BD_DIS   0x100
#define  SC_ODMA_REG_SC_HSV_BD_DIS_OFFSET 9
#define  SC_ODMA_REG_SC_HSV_BD_DIS_MASK   0x200
#define  SC_ODMA_REG_BF16_BD_TYPE   0x100
#define  SC_ODMA_REG_BF16_BD_TYPE_OFFSET 10
#define  SC_ODMA_REG_BF16_BD_TYPE_MASK   0x400
#define  SC_ODMA_REG_SC_CSC_Q_GAIN_MODE   0x100
#define  SC_ODMA_REG_SC_CSC_Q_GAIN_MODE_OFFSET 11
#define  SC_ODMA_REG_SC_CSC_Q_GAIN_MODE_MASK   0x800
#define  SC_ODMA_REG_SC_CSC_R2Y_C00   0x104
#define  SC_ODMA_REG_SC_CSC_R2Y_C00_OFFSET 0
#define  SC_ODMA_REG_SC_CSC_R2Y_C00_MASK   0x3fff
#define  SC_ODMA_REG_SC_CSC_R2Y_C01   0x104
#define  SC_ODMA_REG_SC_CSC_R2Y_C01_OFFSET 16
#define  SC_ODMA_REG_SC_CSC_R2Y_C01_MASK   0x3fff0000
#define  SC_ODMA_REG_SC_CSC_R2Y_C02   0x108
#define  SC_ODMA_REG_SC_CSC_R2Y_C02_OFFSET 0
#define  SC_ODMA_REG_SC_CSC_R2Y_C02_MASK   0x3fff
#define  SC_ODMA_REG_SC_CSC_R2Y_C10   0x108
#define  SC_ODMA_REG_SC_CSC_R2Y_C10_OFFSET 16
#define  SC_ODMA_REG_SC_CSC_R2Y_C10_MASK   0x3fff0000
#define  SC_ODMA_REG_SC_CSC_R2Y_C11   0x10c
#define  SC_ODMA_REG_SC_CSC_R2Y_C11_OFFSET 0
#define  SC_ODMA_REG_SC_CSC_R2Y_C11_MASK   0x3fff
#define  SC_ODMA_REG_SC_CSC_R2Y_C12   0x10c
#define  SC_ODMA_REG_SC_CSC_R2Y_C12_OFFSET 16
#define  SC_ODMA_REG_SC_CSC_R2Y_C12_MASK   0x3fff0000
#define  SC_ODMA_REG_SC_CSC_R2Y_C20   0x110
#define  SC_ODMA_REG_SC_CSC_R2Y_C20_OFFSET 0
#define  SC_ODMA_REG_SC_CSC_R2Y_C20_MASK   0x3fff
#define  SC_ODMA_REG_SC_CSC_R2Y_C21   0x110
#define  SC_ODMA_REG_SC_CSC_R2Y_C21_OFFSET 16
#define  SC_ODMA_REG_SC_CSC_R2Y_C21_MASK   0x3fff0000
#define  SC_ODMA_REG_SC_CSC_R2Y_C22   0x114
#define  SC_ODMA_REG_SC_CSC_R2Y_C22_OFFSET 0
#define  SC_ODMA_REG_SC_CSC_R2Y_C22_MASK   0x3fff
#define  SC_ODMA_REG_SC_CSC_R2Y_ADD_0   0x118
#define  SC_ODMA_REG_SC_CSC_R2Y_ADD_0_OFFSET 0
#define  SC_ODMA_REG_SC_CSC_R2Y_ADD_0_MASK   0xff
#define  SC_ODMA_REG_SC_CSC_R2Y_ADD_1   0x118
#define  SC_ODMA_REG_SC_CSC_R2Y_ADD_1_OFFSET 8
#define  SC_ODMA_REG_SC_CSC_R2Y_ADD_1_MASK   0xff00
#define  SC_ODMA_REG_SC_CSC_R2Y_ADD_2   0x118
#define  SC_ODMA_REG_SC_CSC_R2Y_ADD_2_OFFSET 16
#define  SC_ODMA_REG_SC_CSC_R2Y_ADD_2_MASK   0xff0000
#define  SC_ODMA_REG_SC_CSC_R2Y_FRAC_0   0x11c
#define  SC_ODMA_REG_SC_CSC_R2Y_FRAC_0_OFFSET 0
#define  SC_ODMA_REG_SC_CSC_R2Y_FRAC_0_MASK   0x3ff
#define  SC_ODMA_REG_SC_CSC_R2Y_FRAC_1   0x11c
#define  SC_ODMA_REG_SC_CSC_R2Y_FRAC_1_OFFSET 16
#define  SC_ODMA_REG_SC_CSC_R2Y_FRAC_1_MASK   0x3ff0000
#define  SC_ODMA_REG_SC_CSC_R2Y_FRAC_2   0x120
#define  SC_ODMA_REG_SC_CSC_R2Y_FRAC_2_OFFSET 0
#define  SC_ODMA_REG_SC_CSC_R2Y_FRAC_2_MASK   0x3ff
